The present disclosure relates to the processing of substrates, such as for example, semiconductor substrates. In particular, it provides a novel method to pattern substrates utilizing very narrow pitch techniques, such used in extreme ultraviolet (EUV) lithography.
As geometries in substrate processing continue to shrink, the technical challenges to forming structures on substrates via photolithography techniques increase. As requirements for 36 nm and lower pitch structures arose, a variety of photolithography techniques have been utilized for achieving suitable photolithography for such narrow pitches including EUV lithography (lithography utilizing wavelengths of light in the EUV range, most typically 13.5 nm wavelengths). However, even shifting to EUV lithography, does not solve all of the technical challenges for 36 nm and lower pitch structures. At such small linewidths it is difficult to achieve control over a wide process window. For example, for such narrower pitches, single line open defects are seen even when utilizing EUV lithography. These defects are particularly problematic for the critical dimension (CD) of trench structures formed at the back end of line (BEOL) processing steps. Other processing steps, however, are similarly affected with defects.
It would be desirable to provide a lithography integration technique that allows for tuning of CD control over a wide process window, including at CDs utilized in EUV lithography.